Application of Power-Management Techniques for Low Power Processor Design

The growing demand for mobile and handheld devices requires efficient low-power designs and methodologies providing acceptable levels of performance. This project studies the effects of power-management techniques, specifically clock-gating, for a general-purpose, MIPS-architecture processor. The implementation begins as a behavioral HDL model, and is converted to a synthesized model, for which simulated power-consumption statistics are derived; this process is then be repeated, but with low-power optimizations added. Performance is judged through simulated analysis; however, the completeness of this approach is questioned, and recommendations are provided for a more qualitative analysis, given the resources. Ultimately, this project gives insight into how the proposed low-power technique performs on such a design.